The 72-bit bus width is key because it allows them to interconnect with the new processors in the market that are going toward 64-bit interfaces.
Every fifth clock cycle you have a deterministic message that is sent to the losing port. You monitor the software and it tells you where the issue happened. Then you go directly to that spot and fix it. Previously this was only available in asynchronous memories. When you have a lot of clock skews and rates it becomes a bit more challenging to find collisions.
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