That is the plan for our standard technology. Immersion is still an option that we're looking at for 32-nm.
It will pack about two times as many transistors per unit area and use less power. It will help future products and platforms deliver improved performance.
It does get a little more challenging every time, but we come up with new technology and tricks to keep things going.
This test chip is usually the first significant step we take in developing new logic technologies.
Things have to be faster and lower power, so it's ever-yet more challenging, but we have come up with some new innovations to scale things and keep things on track.
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